1. Technical Field
The present invention relates to electronic circuit design and more particularly, to topology selection of logic gates during synthesis of electronic circuits for minimizing leakage power.
2. Discussion of the Related Art
Static power dissipation is becoming a major design constraint, not only in portable, but also in high performance very large-scale integrated (VLSI) systems. As static power dissipation exceeds dynamic power dissipation in high performance designs, synthesis techniques are being adapted to reduce leakage currents.
Several techniques have been proposed to achieve leakage power reduction based on circuit-level optimization techniques. These techniques require architectural support, and in some cases, technology support, and are applied at run-time (i.e., dynamically) and can be divided into three different categories: (1) input vector control; (2) threshold variation; and (3) power supply gating.
In one example of an input vector control technique, designers introduce sleep transistors to mitigate the increase in leakage current when low-threshold devices are inserted into a design. In this technique, the power and supply terminals of low threshold voltage gates are surrounded by high threshold positive-channel metal oxide semiconductor (PMOS) and negative-channel metal oxide semiconductor (NMOS) transistors, which are normally on in an active mode. In the sleep mode, the high threshold sleep transistors are turned off, thereby limiting the leakage of the high threshold transistors. This technique has a few disadvantages; however, such as decreased circuit speed due to the sleep transistor's resistance and increased area requirements for sleep signals and sleep transistors in a circuit design.
In an example of a threshold variation technique, high threshold devices are placed on non-critical paths and low threshold devices are placed on critical ones. In another threshold variation technique, the body and gate of each transistor are tied together such that whenever the device is off, low leakage is achieved while when the device is on, higher current drives are possible.
In another technique, known as power supply gating, the power supply is shut down so that idle components do not consume leakage power. This can be done by using multi-threshold complementary metal oxide semiconductor (MTCMOS) sleep transistors. The problems associated with this technique are reduced performance and noise immunity if care is not exercised when designing the sleep transistors.
The techniques discussed above attempt to reduce power leakage by performing leakage optimization on components' threshold voltages and/or components' oxide thicknesses. None of these techniques, however, take advantage of the fact that different gate topologies have different gate sensitivities for a unit width of a transistor size to its leakage current as an approach to topology selection.